Circuit SAA3028
De MicElectroLinGenMet.
Voir page Kit Selectronic recepteur RC5 SAA3028
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GENERAL DESCRIPTION
(LE1792 = SAA3028)
The SAA3028 is intended for use in general purpose (RC-5) remote cortrol systems. The main function of this integrated circuit is to convert RC-5 biphase coded signal into equivalent binary values. Two input circuits are available: one for RC-5 coded signal only; the other is selectable to accept (1) RC-5 coded signals only. or (2) (RC-5) (extended) coded signal only. The input used is that at which an active code is first detected. Coded signals flot in RC5/RC-5(ext) format are rejected. Data input and output is by serial transfer, the output interface being compatible for I2C bus operation.
Features
- Converts RC5 or RC-5(ext) biphase coded signaIs into binary equivalents
- Two data inputs, one fixed (RC-5), one selectable (RC-5/RC-5(ext))
- Rejeets all codes not in RC-5/RC-5(ext) format
- I2C output interface capability (Adresse 4Dh)
- Power-off facility
- Master/slave addressable for multi-transmitter/receiver applications in RC-5(ext) mode
- Power-on-reset for defined start-up
QUICK REFERENCE DATA
Supply voltage range: Vdd 4,5 to 5,5 V
Supply current (quiescent) at
Vdd = 5,5V; Tamb = 25°C Idd max. 200 MA
Operating ambient temperature range Tamb -25 to +85°C
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FUNCTIONAL DESCRIPTION
Input function
The two data inputs are accepted into the buffer as folîows:
· DATA 1. Only biphase coded signals which conform to the RC~5 format are accepted at this input.
· DATA 2. This input performs according to the logic state of the select input RC5. When RC5 HIGH, DATA 2 input wiIl accept only RC-5 coded signaIs. When RC5 = LOW, DATA 2 input will accept only RC-5(ext) coded signafs.
The input detector selects the input, DATA 1 or DATA 2, in which a HIGH to LOW transition is first detected. The selected input is then accepted by the buffer for code conversion. AIl signals received that are not in the RC-5 or RC-5(ext) format are rejected.
Formats of RC-5 and RC-5(ext) biphase coded signals are shown in Figs 3 and 4 respectively; the codes commence from the Ieft of the formats shown. The bit-times of the biphase codes are defined in Fig. 5.
More information is added to the input data held in the buffer in order to make it suitable for transmission via the I2C interface. The information now held in the buffer is as follows:
The information assembled in the buffer is subjected to the following controls before being made available at the I2C interface:
ENB = HIGH Enables the set standby input SSB.
SSB = LOW Causes poweroff output PO to go HIGH.
PO = HIGH This occurs when the set standby input SS8 = LOW and allows the existing values in the buffer to be overwritten by the new binary equivalent values. After ENB = LOW, SSB is don't care.
PO = LOW This occurs according to the type of code being processed, as follows:
RC-5. When the binary equivalent value is transferred to the buffer.
RC-5(ext). When the reset standby bit is active and the master address bits are equal in value to the MA0. MA1, MA2 inputs.
At power-on, PO is reset to LOW.
DAV = HIGH This occurs when the buffer contents are valid. If the buffer is not empty, or an output transfer is taking place, then the new binary values are discarded.
Output function
The data is assembled in the buffer in the format shown in Fig. 6 for RC-5 binary equivalent values, or n the format shown in Fig. 7 for RC-5(ext) binary equivalent values. The data is output serially, starting from the left of the formats shown in Figs 6 and 7.
The output signal DAV, derived in the buffer from the data valid bit, is provided to facilitate use of the transcoder on an interrupt basis. This output is reset to LOW during power-on.
The I2C interface allows transmission on a bidirectional, two-wire I2C bus. The interface is a slave transmitter with a buiît-in slave address, having a fixed 7-bit binary value of 0100110.Serial output of the slave address onto the I2C bus starts from the Ieft-hand bit.
Oscillator
The oscillator can comprise a ceramic resonator circuit as shown in Fig. 8. The typical frequency of oscillation is 455 kHz.
I2C bus transmission
Formats for I2C transmission in Iow and high speed modes are shown respectively in Figs 9 and 10.
Note to Figures 9 and 10
When R/W bit = 0; the slave generates a NACK (negative acknowledge), leaves the data line HIGH and waits for a stop (P) condition.
When the receiver generates a NACK; the slave leaves the data line HIGH and waits for P (the slave acting as if all data has been transmitted).
When aIl data has been transmitted, the data line remains HIGH and the slave waits for P.
